Various digital-to-analog converter (DAC) circuits can be employed to generate analog signals from digital codes. Common DAC circuit topologies generally fall into two basic types: voltage scaled and current scaled. Voltage scaling DAC circuits generate an output voltage based on the division and/or multiplication of a reference voltage. Current scaling DAC circuits generate an output current based on the division and/or multiplication of a reference current. Other DAC circuit topologies also exist that are hybrids of current and voltage scaling topologies.
Each digital code consists of a number (N) of binary bits (b1, b2, . . . , bN). The analog output signal (current or voltage) from the DAC corresponds to a particular binary scaling of a full-scale value (FS), where the binary scaling is related to the digital code. The minimum step size for the analog output voltage, between adjacent code words, corresponds to FS/2N and is referred to as a least significant bit (LSB) of resolution. A typical conversion from the N-bit digital code word to an analog signal (current or voltage) yields the following transfer function:
  OUT  =      FS    ×          [                        (                                    b              1                                      2              1                                )                +                  (                                    b              2                                      2              2                                )                +        …        +                  (                                    b              N                                      2              N                                )                    ]      
The above identified equation results in a transfer function with equal step sizes between each adjacent code word, as illustrated by FIG. 1A. However, non-ideal conditions in the DAC implementation may result in non-ideal performance as illustrated by FIGS. 1B–1E. Offset errors are illustrated by FIG. 1B, where the analog voltage associated with each unique binary code has a common offset error for substantially every binary code. Scaling errors (a.k.a. gain errors) are illustrated by FIG. 1C, where the slope of the transfer curve is non-ideal. Linearity errors are illustrated by FIG. 1D, where the slope of the transfer curve changes for at least two adjacent binary codes. Monotonicity errors are illustrated by FIG. 1E, where one or more binary codes yield analog outputs which appear out of sequence.
A binary-weighted current DAC is one topology that includes an array of current sources that are arranged to provide a total output current (Iout) to a load circuit, where the total output current is scaled according to the corresponding digital code. Each current source in the array of current sources is arranged to provide a portion of the total current (Iout) to the load circuit.
The binary-weighted current DAC can be implemented with an array of unequal current sources that are scaled relative to one another to provide the binary weighted currents. The worst code transitions are observed in the transfer function when a single larger current source is activated, and several smaller current sources are deactivated. Non-ideal output current can be observed at these code transitions due to mismatches between the current source elements, resulting in high differential non-linearity (DNL) errors. Mismatches in the relative accuracy of the current sources are often the result of semiconductor processing variations.
A unary current DAC employs a decoder that is arranged to activate unit current sources, all of which have equal value, in sequence as the binary code increases in value. For example, a 9-bit DAC has 512 levels from 0 to 511, where each step corresponds to an additional unit current source. As the binary code increases over the range of the transfer function, additional current sources are activated without deactivating any of the previously active current sources. The unary current DAC provides for excellent linearity, and DNL performance.
Segmented unary DACs employ a combination of techniques for binary weighted DACs and unary DACs. High-order bits are implemented in the unary portion, while low-order bits are implemented in a binary weighted portion. For example, a 9-bit DAC may be implemented as a segmented DAC with bits 1–4 being implemented in a unary fashion, while bits 5–9 may be implemented in a binary fashion. For this example, the unary portion may require 15 unary current sources, while the binary weighted portion may require 5 binary current sources. The segmented unary DAC provides a good tradeoff between the unary and binary-weighted DAC implementations, with overall good DNL and reasonable space requirements (die area).